Semiconductor integrated circuits include an oscillator circuit configured to output a clock signal with a constant frequency for in-circuit time setting. One example of such an oscillator circuit includes an oscillator circuit using a comparator.
Comparators are one of the elements, and Patent Document 1 describes a comparator as one example.
Some oscillator circuits using a comparator include external resistor and capacitor connecting to one of the input terminals of the comparator, and change a reference voltage input to the other input terminal of the comparator depending on the output of the comparator. Such an oscillator circuit has an oscillatory frequency that is determined by the resistance value and the capacitance value of the external resistor and capacitor, and by the reference voltage.
FIG. 27 illustrates a conventional oscillator circuit using a comparator. An oscillator circuit 1 includes: a power-supply terminal VDD to receive an external power-supply voltage; an input terminal CG connecting to external resistor R0 and capacitor C0 to determine the oscillatory frequency; and a ground terminal GND connecting to the ground level. In this drawing, VDD indicates the power-supply voltage as well. The input terminal CG also functions as the input terminal to receive an external control signal to control the comparator and thus the oscillator circuit.
The oscillator circuit 1 also includes a comparator having a differential unit 2 and a gain unit 3 each connecting to the power-supply terminal VDD and the ground terminal GND, and a transistor (P-type MOSFET) P5 connecting to the power-supply terminal VDD and the ground terminal GND. The drain of the transistor P5 connects to a constant current source to flow a constant current “ibias”.
The differential unit 2 includes transistors (P-type MOSFETs) P2 to P4 and transistors (N-type MOSFETs) N3 and N4. The drain of the transistor P5 connects to the gate of this transistor and to the gate of the transistor P2. The sources of the transistors P5 and P2 connect to the power-supply terminal VDD. The transistors P5 and P2 make up a current mirror circuit, and the transistor P2 serves as a constant current source that supplies a bias current to the differential unit 2, where the constant current “ibias” flowing through the transistor P5 is the reference current of the bias current (i.e., the bias current is proportional to the constant current “ibias”).
The drain of the transistor P2 connects to the sources of the transistors P3 and P4 that make up a differential pair. The gates of the transistors P3 and P4 are the input of the differential unit 2. The gate of the transistor P3 receives the electric potential at the connecting point of the resistor R0 and the capacitor C0, or a control signal via the input terminal CG. The gate of the transistor P4 receives a reference voltage to be compared with the electric potential at the connecting point of the resistor R0 and the capacitor C0 or with the control signal input from an external circuit. The drain of the transistor P3 connects to the drain of the transistor N3. The drain of the transistor P4 connects to the drain and the gate of the transistor N4 and to the gate of the transistor N3. The sources of the transistors N3 and N4 connect to the ground terminal GND. The transistors N3 and N4 make up a current mirror circuit, and serve as an active load of the differential unit 2. The drain of the transistor P3 and the drain of the transistor N3 are the output of the differential unit 2.
The gain unit 3 includes a transistor (P-type MOSFET) P1 and a transistor (N-type MOSFET) N2 as an amplifier. A constant current flows through the transistor P1, and the constant current “ibias” is the reference current of this constant current (i.e., this constant current is proportional to the constant current “ibias”). The source of the transistor P1 connects to the power-supply terminal VDD, and the gate of this transistor connects to the drain of the transistor P5 and to the gate of the transistor P5. The transistors P5 and P1 make up a current mirror circuit. The drain and the source of the transistor N2 connect to the drain of the transistor P1 and the ground terminal GND, respectively. The gate of the transistor N2 receives the output of the differential unit 2. The connecting point of the drain of the transistor P1 and the drain of the transistor N2 is the output of the gain unit 3.
The oscillator circuit 1 also includes: a voltage-dividing circuit having resistors R2 to R6 that are serially connected in sequence between the power-supply terminal VDD and the ground terminal GND; and switches (N-type MOSFETs) N5 and N6. This voltage-dividing circuit yields a first reference voltage V1 that is a voltage at the connecting point between the resistor R3 and the resistor R4, and a second reference voltage V2 that is a voltage at the connecting point between the resistor R4 and the resistor R5. The second reference voltage V2 is lower than the first reference voltage. The first reference voltage V1 is input to the gate of the transistor P4 via the switch N5. The second reference voltage V2 is input to the gate of the transistor P4 via the switch N6 that operates in the opposite phase of the switch N5.
The comparator includes inverters INV1 and INV2 in addition to the differential unit 2 and the gain unit 3. The output of the gain unit 3 is input to the inverter INV2. The output of this inverter INV2 is input to the inverter INV1 and to the gate of the switch N5. The output of this inverter INV1 connects to the gate of the switch N6. The output of the inverter INV1 is the output of the comparator.
The oscillator circuit 1 also includes a discharge circuit to discharge the capacitor C0. The discharge circuit includes: a resistor R1 and a transistor (N-type MOSFET) N1 serially connected between the input terminal CG and the ground terminal GND. The gate of the transistor N1 receives the output of the comparator. A D-type flip-flop circuit D-FF frequency-divides the comparator output so that the resultant frequency is ½ and the resultant duty ratio is 50%, and the output after such frequency-dividing is the clock output (the output of the oscillator circuit 1).
For typical operation of such an oscillator circuit 1, the oscillator circuit includes a resistor R0 externally connecting to the input terminal CG and the power-supply terminal VDD. The oscillator circuit also includes a capacitor C0 externally connecting to the input terminal CG and the ground terminal GND. In this case, charge-discharge of the capacitor C0 yields a control signal to be input to the input terminal CG.
In one example, let the power-supply voltage be 5 V, and the reference potential of the oscillator circuit 1 be at the ground level, i.e., 0 V. The resistors R2 to R6 have the same resistance values. This means that the first reference voltage V1 is 3 V, and the second reference voltage V2 is 2 V. All logical threshold voltages for the inverter INV1, the inverter INV2, and the D-type flip-flop circuit D-FF are ½×VDD. The resistance value of the resistor R1 is sufficiently smaller than the resistance value of the resistor R0. The resistance value of the resistor R0 and the capacitance value of the capacitor C0 are set so that the oscillatory frequency of the comparator output is about 200 kHz, i.e., the frequency of the clock output is about 100 kHz. The gate threshold voltage of the transistor N2 is set at 0.7 V.
FIGS. 28(a)-28(e) illustrate simulated waveforms of the voltage at various parts of the oscillator circuit 1 during typical operation. The horizontal axis in this drawing indicates time (μs). The vertical axis indicates CG voltage (V) that is the voltage at the input terminal CG in FIG. 28(a), output voltage of the differential unit (V) in FIG. 28(b), output voltage of the gain unit (V) in FIG. 28(c), comparator output voltage (V) in FIG. 28(d), and clock output voltage (V) in FIG. 28(e).
When the comparator output voltage is at a low level (0 V), the output of the inverter INV1 is at a low level and the output of the inverter INV2 is at a high level. This turns the switch N5 on and the switch N6 off. The reference voltage input to the differential unit 2 therefore is the first reference voltage V1, i.e., 3 V. The transistor N1 also turns off. This charges the capacitor C0 with a charge current Ic illustrated in FIG. 27, so that the CG voltage increases from 2 V to 3 V. At this time, the output voltage of the differential unit is at a high level. The transistor N2 in the gain unit 3 therefore turns on, and the output voltage of the gain unit is at a low level (0 V).
When the CG voltage exceeds the first reference voltage V1, i.e., 3 V, the current flowing through the transistor P4 exceeds the current flowing through the transistor P3, so that the gate voltage of the transistors N3 and N4 increases. The output voltage of the differential unit gradually decreases while discharging the Miller capacitance between the gate and the drain of the transistor N2 and the gate capacitance of this transistor via the current flowing through the transistor N3.
Note here that the capacitance (parasitic capacitance) between the gate and the drain of the transistor N2 acts while having the magnitude multiplied by the voltage amplification factor of the transistor (strictly multiplied by (the voltage amplification factor+1)). This phenomenon is called the Miller effect. The value obtained by multiplying the capacitance between the gate and the drain by the voltage amplification factor of the transistor is called the Miller capacitance between the gate and the drain.
When the output voltage of the differential unit falls below the gate threshold voltage of the transistor N2, then the transistor N2 turns off. The output voltage of the gain unit then gradually increases while charging the Miller capacitance between the gate and the drain of the transistor N2 via the constant current from the transistor P1.
When the output voltage of the gain unit reaches the logical threshold voltage of the inverter INV2, then the output voltage of the inverter INV2 changes to a low level. The output voltage of the inverter INV1, i.e., the comparator output voltage changes to a high level (5 V). This turns the switch N5 off and the switch N6 on. The reference voltage input to the differential unit 2 therefore is the second reference voltage V2, i.e., 2 V. Turning on the transistor N1 discharges the capacitor C0. That is, as illustrated in FIG. 27, a discharge current Id flows from the capacitor C0 to the ground terminal GND via the input terminal CG, the resistor R1, and the transistor N1. This lowers the CG voltage.
When the CG voltage falls below the second reference voltage V2, i.e., 2 V, the current flowing through the transistor P3 exceeds the current flowing through the transistor P4 and the current flowing through the transistor P4 decreases, so that the gate voltage of the transistors N3 and N4 decreases. The output voltage of the differential unit changes to a high level. The transistor N2 therefore turns on, and the output voltage of the gain unit changes to a low level (0 V). The output voltage of the inverter INV2 change to a high level, and the output voltage of the inverter INV1, i.e., the comparator output voltage changes to a low level (0 V). This turns the switch N5 on and the switch N6 off. The reference voltage input to the differential unit 2 therefore is the first reference voltage V1, i.e., 3 V. The transistor N1 also turns off. This charges the capacitor C0 with the charge current Ic, so that the CG voltage increases.
Such an operation is repeated, so that the comparator output has the rectangular waveforms having the frequency determined by the resistance value of the resistor R0, the capacitance value of the capacitor C0, the first reference voltage V1 and the second reference voltage V2 (FIG. 28(d)). The D-type flip-flop circuit D-FF frequency-divides the comparator output so that the resultant frequency is ½ and the resultant duty ratio is 50%, and the output after such frequency-dividing is the clock output (FIG. 28(e)).
FIG. 29 illustrates the configuration to conduct an inspection before shipment of a semiconductor integrated circuit including a digital circuit operating with the clock output of the oscillator circuit 1. In FIG. 29, like reference numerals indicate like parts in FIG. 27, and their detailed descriptions are omitted. To conduct the inspection before shipment, a rectangular-wave generation circuit 9 is externally connected to the input terminal CG, instead of the resistor R0 and the capacitor C0. This rectangular-wave generation circuit 9 is to input a rectangular-wave control signal to the input terminal CG, the rectangular-wave control signal having a frequency higher than the oscillatory frequency determined by the resistance value of the resistor R0 and the capacitance value of the capacitor C0. Such inputting of a control signal with a relatively high frequency is to overclock the clock output of the oscillator circuit 1 and to shorten the time required for the inspection before shipment of the semiconductor integrated circuit.
FIGS. 30(a)-30(e) illustrate simulated waveforms of the voltage at various parts of the oscillator circuit 1 when the rectangular-wave control signal by the rectangular-wave generation circuit 9 is input to the input terminal CG. As illustrated in FIG. 30(a) in the drawing, the rectangular waves have the amplitude between 0 V and 5 V, and have the frequency of 2 MHz. That is, the period of the rectangular waves is 500 ns.
When the CG voltage rises from a low level (0 V) to a high level (5 V), then the output voltage of the differential unit gradually decreases while discharging the Miller capacitance between the gate and the drain of the transistor N2 and the gate capacitance of this transistor via the current flowing through the transistor N3. In FIG. 30(b), “K51” denotes this.
When the output voltage of the differential unit falls below the gate threshold voltage of the transistor N2, then the transistor N2 turns off. The output voltage of the gain unit then gradually increases while charging the Miller capacitance between the gate and the drain of the transistor N2 via the constant current from the transistor P1. In FIG. 30(c), “K52” denotes this.
In this way, rising of the CG voltage decreases the output voltage of the differential unit and increases the output voltage of the gain unit. The CG voltage, however, falls before the output voltage of the gain unit reaches the logical threshold voltage (2.5 V) of the inverter INV2. Falling of the CG voltage decreases the output voltage of the gain unit as well, so that the output voltage of the gain unit finally changes to a low level.
That is, the output voltage of the gain unit does not reach the logical threshold voltage (2.5 V) of the inverter INV2 through the entire period. The comparator output voltage therefore is fixed to a low level (0 V) through the entire period, and so the oscillation does not occur. The clock output voltage therefore is fixed to a high level (5 V) (in the case of FIG. 30(e)) or to a low level (0 V) through the entire period, and so the oscillation does not occur.
In this way, the comparator output voltage fails to follow the rectangular-wave control signal with 2 MHz from the rectangular-wave generation circuit 9, i.e., overclocking to 2 MHz fails.